Customer Use-Case:
- An algorithm has already been developed and validated
- The deployment into an FPGA requires special know-how and tremendous effort
- The framework includes the following FPGA IPs:
- Tested ADC/DAC IPs to interface to commercially available components with SPI, LVDS, and JESD204B interface
- IP to seamlessly implement a control state machine with pre-defined commands
- IP to support FT245 style asynchronous/synchronous FIFO for data transfer
- IP to implement proper algorithm synchronization with both external and internal triggers
- Our methodology:
- Our engineering team defines a system-level architecture in collaboration with the Customer
- Once the architecture is agreed we configure the required IPs to meet the design requirements
- For custom development, we provide separate effort estimation and do the coding in-house
- A self-checking testbench is developed to allow system and integration level simulation
- After simulation, the system is verified on a HIL testbench
- The Customer team receives regular updates including sources and configured IDE project – at major milestones we provide tested releases
- Target FPGAs:
- Xilinx 7 series and Ultrascale devices
- Microchip FPGA devices
- Intel FPGA devices
